pacino · microarchitecture
8-issue OoO · RVA23S64 · decoupled frontend / OoO backend
done
active
planned
Frontend
BPU
FTQ
IFU / I$
Predecode
IBuf
Decode
→
Midcore
Rename
Dispatch
ROB
PRF
Issue queues
→
Execution
Int ALU
FPU
Vec (RVV)
Matrix
Atomics
LSU
→
Memory
L1D + DTLB
L2 + L2TLB
L3 + prefetch
MMU / PTW
PMA / PMP
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