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// overview

"I'm out of order? You're out of order!"

Pacino is an open source 8-issue out-of-order RISC-V processor targeting the RVA23S64 profile. RTL is written in SystemVerilog, simulated with Verilator, and verified with a combination of directed tests, functional coverage, formal analysis via SymbiYosys and riscv-formal, and spike-dasm as an independent oracle. Gate synthesis targets Yosys with FPGA mapping via Quartus and Vivado. Design decisions, AI-assisted co-design records, and architectural rationale are committed alongside the RTL.

// specs

architecture

RISC-V RVA23S64

issue width

8-issue OOO

rtl language

SystemVerilog

simulator

Verilator 5.x

compiler

GCC 16.x, LLVM 22.x RISC-V

status

active

// architecture

frontend

icache · ftq · ifu · ibuf · decode · bpu

dispatch

rename · prf (i/f/v/mm) · rob · reservation stations

execute

int · float · vector · matrix · atomics

lsu

agu · lq · sq · fwd · l1d · vlsu · mmlsu

memory

l2 · l3 · prefetch

mmu

itlb · dtlb · l2tlb · ptw

uncore

tilelink · csr · pmu · trace

protection

pma · pmp

// ai co-design methodology

Pacino is designed using a structured AI co-design methodology — a domain expert directing a dual-agent workflow across architectural planning and RTL implementation. Prompts, iteration history, and design rationale are committed alongside the RTL as first-class artifacts. Full methodology documentation is in the FAQ and the repo.

// get started

view on github ↗ read the docs ↗ read the FAQ ← uarchlabs