pacino
Out-of-order RVA23 RISC-V processor — design flow and RTL. The uarchLabs co-design flow is currently tightly coupled to RVA23-based microarchitectures like pacino. As the uarchlabs portfolio grows, the flow will be abstracted into a standalone tool.
active RISC-V RVA23 out-of-order SystemVerilog open source
● active
+ next project · coming soon
// mission
Open source hardware design organization. Building processors and design flows in the open, with AI co-design methods documented end-to-end — prompts, loops, and rationale included.
// license
All RTL and tooling released under open source licenses. Synthesizable, forkable, yours.