uarchlabs is an open source hardware design organization. We build high performance processors and publish everything — the RTL, the design decisions, and the AI-assisted methodology used to produce them.
The first project is Pacino: an 8-issue out-of-order RISC-V processor targeting the RVA23S64 profile with competitive SPECint2006 performance as the design goal. The target is deliberately ambitious — a simple pipeline would not stress the methodology.
This blog series documents the design and the process. Posts cover architectural decisions, experiment results, and the AI co-design flow as it develops. The methodology, the prompts, the success and failures, and the results will be published. We are making transparency part of the point.
The next post covers the project rationale, methodology, and workflow in detail. A FAQ covering scope, tooling, and design targets is at uarchlabs.com/faq.html.
Jeff Nye is a microprocessor architect with 35 years of industry experience spanning performance modeling, RTL implementation, and architecture for high-performance OOO processors. He has contributed RTL to Pentium 4, ARM V7, TI C6x and RISC-V designs, and recently served as sole architect and full-stack implementer of the TAGE-SC-L + ITTAGE branch prediction cluster in an 8-issue RVA23 RISC-V processor — from research through timing closure at 2.75 GHz. He holds 20+ issued patents in processor design, architecture, and hardware virtualization.
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