// blog

BPU Series ITTAGE -- Table, Controller, Wrapper, and First Integrated Testbench

ITTAGE RTL implementation across 6 sessions.

BPU Series ITTAGE Design and Planning

Seven research questions answered, planning documents drafted. Process difficulties documented and resolved.

BPU Series TAGE Coverage Methodology and Closure

Building a Verilator coverage pipeline and applying it to close TAGE.

BPU Series TAGE Arbitration and Integration

Beginning of the BPU arbitration implementation and parameter consistency edits that will carry forward for ITTAGE and SC.

BPU Series TAGE Verification

4 IA sessions covering TAGE verification, 4 RTL bugs found and fixed, completing the round-trip unit testing.

BPU Series TAGE Implementation

The TAGE implementation and unit testing, in 12 IA sessions.

BPU Series TAGE -- Architecture and the Decomposition Problem

The TAGE sessions introduced a different class of problem, the architecture of structure.

BPU Series When the Tools Fail: Hidden Limits in AI-Assisted Hardware Design

Hitting tools limits -- and searching for a fix that did not exist.

BPU Series Iteration Counting at s1: The Loop Predictor

The loop predictor is the second s1-stage predictor in the branch predictor (BP) cluster

BPU Series Branch History and the First Prediction

The history module is the centralized owner of all branch history state.

BPU Series Branch Prediction Cluster Organization

Building a Seven-Predictor Branch Prediction Cluster for RVA23

RVA23 Support Memory disambiguation and pre-decode

Last of the decoder track covering memory disambiguation, pre-decode and what comes next

RVA23 Support Scalar Foundation to Vector ALU

From the first scalar instruction through 168 vector ALU enum entries and 453 passing tests

RVA23 Support What RVA23 Actually Asks of a Decoder

The mandatory extension list for RVA23S64 is not short. A discussion of the profile and decoding nuances.

Pacino and uarchlabs Project Rationale

The emergence of LLMs raises a practical question for high performance large-scale processor development: can a standards-compliant, competitively performant...

Announcement Introducing uarchlabs and the Pacino blog series

uarchlabs is an open source hardware design organization. We build high performance processors and publish everything — the RTL, the design decisions, and th...