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Pacino
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Instruction Fetch
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Fetch Target Queue
Branch Detector
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Decode
Decode
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RVC Expander
Fusion Combiner
Integer Decode
Float Decode
Vector Decode
Branch Prediction Unit
Branch Prediction Unit
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uBTB
TAGE
Statistical Corrector
Fetch Target Buffer
Loop Predictor
ITTage
Return Address Stack
History Module
Dual Prediction
Backend
Backend
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Rename
Rename
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Register Alias Table
Architectural Register Map Table
Free List
Dispatch and ROB
Dispatch and ROB
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Dispatch
Reorder Buffer
Scheduling and Issue
Scheduling and Issue
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Scheduler
Scoreboard
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Issue Select Logic
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Wakeup
Register Files and Bypass
Register Files and Bypass
Physical Register Files
Register Read
Bypass Network
Writeback Data Path
Execute
Execute
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Integer Functional Units
Float Functional Units
Vector Functional Units
Matrix Functional Units
Memory Subsystem
Memory Subsystem
Load/Store Unit
Load/Store Unit
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Address Generation Unit
Load Unit
Store Address Unit
Store Data Unit
Atomic Operation Unit
Misaligned Unit
Uncached Access Unit
Load/Store Queue
Load/Store Queue
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Memory Ordering and Forwarding
Load Queue
Store Queue
Store Buffer
Exception Buffer
Uncache Buffer
Vector Load/Store Unit
Vector Load/Store Unit
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VSplit
VMerge
Vector Segment Unit
Misalign Buffer
Vector FOF Buffer
Cache Subsystem
Cache Subsystem
Data Cache
Data Cache
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Tags
Data Arrays
Load Pipeline
Main Pipeline
Miss Queue
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Coherency Logic
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L2 Cache
L2 Cache
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Channel A Request Buffer
Request Arbiter and Main Pipeline
Directory
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MSHR
Upstream TileLink Channels
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MMIO Bridge
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MMU
MMU
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L1 TLB
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L2 TLB
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Page Table Walker
Last Level Page Table Walker
Hypervisor Page Table Walker
Miss Queue
Prefetcher
PMP
PMA
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System
CSR
Exceptions and Traps
Hardware Performance Monitor
Debug Module
Scheduling and Issue
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