Showcase

A showcase release is documentation built around testcases and waveforms. Each page follows one program through the RTL and explains what the waveform shows. It is not a specification; the design is described in the architecture pages and the planning documents.

Release 01: Frontend Demo

Twenty-four short programs run on the Pacino frontend, fe_top, with testbench models of the backend, the page table walker and memory. Each scenario shows one behavior: prediction and override, the predictors, redirects, the L1I, translation and faults, compressed code, uncached fetch, cache maintenance, backpressure and commit. Each run ends in a PASS or FAIL line and writes an FST waveform. The Frontend Overview describes the design. How a Scenario Is Built and Run covers the testbench, the program writer and how to read the waveforms.

Select either diagram to open it at full size. The signal annotations on the block view refer to the fe_top connectivity inventory.

Running it

From examples/fe_demo/:

make <scenario>          run one scenario; writes out/<scenario>/
make scenarios           run all 24 in order
make view S=<scenario>   open the scenario's waveform in Surfer
make help                list the scenarios

It needs Verilator 5.048 and, for make view, Surfer; the repository README covers installing both.

Scenarios

Each scenario's waveform opens in Surfer in the browser, with nothing to install.

FD	Scenario	What it shows	Waveform
1	Reset and SRAM Initialization	The TAGE, ITTAGE and SC init walks; no p0 request until all three are ready	Open
2	Steady-State Prediction and Fetch	Straight-line code: one FTQ entry and eight decoded instructions per cycle	Open
3	Two Branches in One Block	p1 and p2 predictions with both prediction slots valid	Open
4	p2 Override	A uBTB miss corrected by the FTB at p2	Open
5	p3 Override	The statistical corrector reversing TAGE at p3	Open
6	Loop Predictor	The loop predictor learning a trip count and predicting the exit	Open
7	Calls and Returns	RAS push and pop, recursion count and return-call	Open
8	Indirect Jump	ITTAGE supplying history-dependent indirect targets	Open
9	TAGE Provider, Allocation and use_alt_on_na	A tagged-table provider, allocation after a mispredict, and use_alt_on_na	Open
10	Predecode Redirect	Predecode at F3 finding an unpredicted JAL and redirecting fetch	Open
11	Backend Mispredict	A backend redirect: FTQ squash, IFU flush, history and RAS recovery	Open
12	Predictor Training and the FTB Update Bubble	Updates to every predictor, and the p0 request each FTB update withholds	Open
13	L1I Hit, Miss and MSHR Merge	L1I hits, misses with fills, and a request merging onto an MSHR	Open
14	Sv39 Walk, Sv39x4 Nested Walk and Svadu CAS	A single-stage walk, a two-stage walk at V=1, and an A-bit update by CAS	Open
15	Page, Access and Guest-Page Fetch Faults	The three fetch faults carried with their blocks to decode	Open
16	A Fetch Block Crossing a Page	One fetch block translated twice, with an instruction straddling the pages	Open
17	Compressed and Unaligned Code	A 32-bit instruction straddling two blocks, and 16-bit control transfers	Open
18	Uncached Fetch	Fetch from PBMT NC and IO pages, never filled into the L1I	Open
19	FENCE.I and cbo.inval	L1I invalidation and the fetch restart after each	Open
20	Backpressure	A slow backend stalling decode, the IBUF, the IFU and the FTQ in turn	Open
21	Commit	The FTQ commit pointer and the RAS commit stack	Open
22	SC Reversing Slot 1	The statistical corrector reversing the branch in slot 1 at p3	Open
23	A Jump Behind Two Conditionals	The FTB splitting a block that holds two conditionals and a jump	Open
24	A Call in Slot 1	A RAS push from slot 1 behind a not-taken conditional	Open

FD-3 and FD-22 to FD-24 run on the two-slot build; the rest on the one-slot build.