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Pacino

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Pacino

uarchlabs/pacino

Home
Overview
IA Tasks
Frontend
Frontend
- Overview
- Instruction Cache
  Instruction Cache
  - Overview
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Showcase
Showcase
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Backend
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  Dispatch and ROB
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Memory Subsystem
Memory Subsystem
- Load/Store Unit
  Load/Store Unit
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  Load/Store Queue
- Vector Load/Store Unit
  Vector Load/Store Unit
Cache Subsystem
Cache Subsystem
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  Data Cache
- L2 Cache
  L2 Cache
MMU
MMU
- Overview
- L1 TLB
- L2 TLB
  L2 TLB
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System
System

Data Cache¶

Not written yet

Status: RTL planned. Documentation planned.

This page will cover the L1 data cache, its organization and pipelines.

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