Instruction Cache

Not written yet

Status: RTL complete. Documentation planned.

This page will cover the L1 instruction cache generated by cachegen, its organization, hit and miss paths, and maintenance operations.

Meanwhile:

• IA tasks: TOOLS-004, TOOLS-005, BP-123
• Frontend demo: fd13_l1i: L1I Hit, Miss and MSHR Merge
• Frontend demo: fd19_fencei_cbo: FENCE.I and cbo.inval