Skip to content
Pacino
Vector Segment Unit
Initializing search
uarchlabs/pacino
Home
Overview
Frontend
Backend
Memory Subsystem
Cache Subsystem
MMU
System
Pacino
uarchlabs/pacino
Home
Overview
Frontend
Frontend
Overview
Instruction Cache
Instruction Cache
Overview
Tags
Data Arrays
I-TLB
PLRU
Victim Buffer
MSHRs
Prefetcher
IL2 Interface
Instruction Fetch
Instruction Fetch
Overview
Fetch Target Queue
Branch Detector
Pre-Fusion Detector
Decode
Decode
Overview
RVC Expander
Fusion Combiner
Integer Decode
Float Decode
Vector Decode
Branch Prediction Unit
Branch Prediction Unit
Overview
uBTB
TAGE
Statistical Corrector
Fetch Target Buffer
Loop Predictor
ITTage
Return Address Stack
History Module
Dual Prediction
Backend
Backend
Overview
Rename
Rename
Overview
Register Alias Table
Architectural Register Map Table
Free List
Dispatch and ROB
Dispatch and ROB
Overview
Dispatch
Reorder Buffer
Scheduling and Issue
Scheduling and Issue
Overview
Scheduler
Scoreboard
Reservation Stations
Issue Queues
Issue Select Logic
Speculative Issue
Wakeup
Register Files and Bypass
Register Files and Bypass
Physical Register Files
Register Read
Bypass Network
Writeback Data Path
Execute
Execute
Overview
Integer Functional Units
Float Functional Units
Vector Functional Units
Matrix Functional Units
Memory Subsystem
Memory Subsystem
Load/Store Unit
Load/Store Unit
Overview
Address Generation Unit
Load Unit
Store Address Unit
Store Data Unit
Atomic Operation Unit
Misaligned Unit
Uncached Access Unit
Load/Store Queue
Load/Store Queue
Overview
Memory Ordering and Forwarding
Load Queue
Store Queue
Store Buffer
Exception Buffer
Uncache Buffer
Vector Load/Store Unit
Vector Load/Store Unit
Overview
VSplit
VMerge
Vector Segment Unit
Misalign Buffer
Vector FOF Buffer
Cache Subsystem
Cache Subsystem
Data Cache
Data Cache
Overview
Tags
Data Arrays
Load Pipeline
Main Pipeline
Miss Queue
Probe Queue
Writeback Queue
Victim Queue
Coherency Logic
Error Handling
L2 Cache
L2 Cache
Overview
Channel A Request Buffer
Request Arbiter and Main Pipeline
Directory
Data SRAM
MSHR
Upstream TileLink Channels
Downstream CHI Channels
MMIO Bridge
Error Handling
MMU
MMU
Overview
L1 TLB
L2 TLB
L2 TLB
Page Cache
Page Table Walker
Last Level Page Table Walker
Hypervisor Page Table Walker
Miss Queue
Prefetcher
PMP
PMA
System
System
CSR
Exceptions and Traps
Hardware Performance Monitor
Debug Module
Vector Segment Unit
¶
Back to top