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Pacino

Miss Queue

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Pacino

uarchlabs/pacino

Home
Overview
IA Tasks
Frontend
Frontend
- Overview
- Instruction Cache
  Instruction Cache
  - Overview
  - Tags
  - Data Arrays
  - I-TLB
  - PLRU
  - Victim Buffer
  - MSHRs
  - Prefetcher
  - IL2 Interface
- Instruction Fetch
  Instruction Fetch
- Decode
  Decode
- Branch Prediction Unit
  Branch Prediction Unit
Showcase
Showcase
- Frontend Demos
  Frontend Demos
Backend
Backend
- Overview
- Rename
  Rename
- Dispatch and ROB
  Dispatch and ROB
- Scheduling and Issue
  Scheduling and Issue
- Register Files and Bypass
  Register Files and Bypass
- Execute
  Execute
Memory Subsystem
Memory Subsystem
- Load/Store Unit
  Load/Store Unit
- Load/Store Queue
  Load/Store Queue
- Vector Load/Store Unit
  Vector Load/Store Unit
Cache Subsystem
Cache Subsystem
- Data Cache
  Data Cache
- L2 Cache
  L2 Cache
MMU
MMU
- Overview
- L1 TLB
- L2 TLB
  L2 TLB
- PMP
- PMA
System
System

Miss Queue¶

Not written yet

Status: RTL planned. Documentation planned.

This page will cover the L1D miss queue and miss merging.

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